1. Field of the Invention
The present invention relates to a technology for creating a simplified false-path description on a false path detected in a target circuit.
2. Description of the Related Art
In designing a circuit of a semiconductor device such as a large scale integration (LSI), a timing analysis is executed to estimate circuit delay and to check whether the estimated circuit delay is within a range of delay that is necessary for the normal operation of a target circuit included in the LSI or a part of the LSI. This timing analysis is an indispensable step for securing a designed circuit to operate accurately and for optimizing a clock operation, and not only a netlist of the target circuit but also a description on a timing exception (such as a false path), etc., are necessary.
FIG. 10 is a schematic of a false path in a target circuit. A target circuit 1000 includes combinational circuits 1001, 1002, 1003, and 1004, multiplexers 1005 and 1006, and a NOT gate 1007.
Each of the combinational circuits 1001, 1002, 1003, and 1004 is a circuit formed by combining logic circuits. The combinational circuits 1001, 1003 are circuits that need a processing time period of 3 nanoseconds (ns), respectively. The combinational circuits 1002, 1004 are circuits that need a processing time period of 1 ns, respectively.
The multiplexers 1005, 1006 switch paths based on an input signal. Specifically, each of the multiplexers causes a path from an input A to pass through when an input signal from an input C is “0”, and causes a path from an input B to pass through when the input signal from the input C is “1”. The NOT gate 1007 is a logic gate that inverts an input signal. Specifically, the NOT gate 1007 sets an output signal of “1” when an input signal is “0”, and sets an output signal of “0” when an input signal is “1”.
A target path 1010 indicated by a thick line in the target circuit 1000 is a false path on which no combination of inputs for transmitting a signal is present. Specifically, the multiplexer 1005 causes the input A to pass through when an input signal from the input C in the multiplexer 1005 is “0”. However, the input signal from the input C in the multiplexer 1006 becomes “1” due to the NOT gate 1007. Therefore, the multiplexer 1006 does not cause the input A to pass through.
Furthermore, when an input signal from the input C in the multiplexer 1006 is “0”, the multiplexer 1006 causes the input A to pass through. However, the input signal from the input C in the multiplexer 1005 is “1” due to the NOT gate 1007. Therefore, the multiplexer 1005 does not cause the input A to pass through.
In the timing analysis of the target circuit 1000, circuit delay is estimated by detecting the false path described above. Specifically, in the target circuit 1000, the maximum processing time of 6 ns may be necessary when a signal passes through the target path 1010. However, this can be ignored because no signal transmits through the path 1010, and the circuit delay can be estimated to be 4 ns. More specifically, the processing time of 4 ns of a path passing through the combinational circuit 1001 and the combinational circuit 1004 or of a path passing through the combinational circuit 1002 and the combinational circuit 1003 is the circuit delay.
As to detection of a false path, a method of checking whether a path in a target circuit is a false path based on a satisfiablity check, has been proposed (for example, Japanese Patent Application Laid-Open Publication No. 2003-526149). A method of improving the speed of judging a false path by simplifying a pattern input to a path for the judgment has been also proposed (for example, Japanese Patent Application Laid-Open Publication No. 2001-67383).
Reduction of processing time in detecting a false path and processing time of a tool that utilizes information on detected false path by directly detecting passing points of signal lines in a target circuit has been proposed (for example, Japanese Patent Application Laid-Open Publication No. 2005-149373).
Recently, a target circuit of an LSI or a part of an LSI has become more complicated due to an increase in the number of logic gates therein. As a result, the number and the data amount of descriptions on the detected false paths become tremendous even when detection of a false path using the conventional technologies is executed.
Therefore, tremendous processing time is necessary to execute timing analyses and to execute optimization of the layout of circuit designing, etc., for each of the tremendous number of descriptions on false paths, thereby increasing a period for the designing.
Furthermore, with only the descriptions on the false paths output, check on an input signal must be executed for all the pieces of the descriptions. It increases labor of and a load on design engineers, especially when the number of the pieces of the descriptions are large or the pieces of the descriptions cause a conflict in an indirect manner.